The present invention relates generally to semiconductor manufacture and, more particularly, to a method for fabricating reliable interconnect structures in semiconductor integrated circuits, and more particularly to protection of the interconnecting structures using a protective metallic film.
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) devices having diffused source and drain regions that are separated by channel regions, and gates that are located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as CMOS transistors.
Conventionally, a dielectric layer (e.g., silicon dioxide) is deposited over the devices that are formed on a substrate, and via holes are formed through the dielectric layer to the devices below. As is well known in the art, photolithography xe2x80x9cpatterningxe2x80x9d is typically accomplished by depositing a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having via hole patterns, developing the photoresist to form a photoresist via mask, and etching the exposed dielectric layer to form the via holes that lead to a lower level. Once the via holes are formed, a conductive material such as tungsten (W) is used to fill the via holes to define what are known as xe2x80x9ctungsten plugs.xe2x80x9d Once the tungsten plugs are formed, a metallization layer is formed over the dielectric layer and the tungsten plugs. The metallization layer is then patterned using conventional photolithography and plasma etching techniques to define a first level of interconnect metal routing. This process may then be repeated if additional layers of interconnect structures are desired.
To facilitate discussion, a semiconductor substrate will typically have a number of layers fabricated thereon. In this example, the semiconductor substrate has a first dielectric layer deposited over its surface, and a first metallization layer patterned over the first dielectric layer. A second dielectric layer is then deposited over the first dielectric layer and the first metallization layer. Before a second metallization layer is patterned over the second dielectric layer, via holes are etched and filled with a tungsten material to form tungsten plugs. At this point, the second metallization layer is plasma etched to define the desired interconnect lines.
As is well known, conventional plasma etching will cause the semiconductor substrate to be negatively charged, and all metallization features and tungsten plugs (i.e., unless they are coupled to the substrate) to be positively charged. Once the plasma etching is complete, the substrate is conventionally moved to a basic solution cleaning station where it is submerged in an effort to remove any polymer residues produced during the plasma etching.
Although the basic solution submersing works well in removing the polymer residues, if any one of the tungsten plugs are exposed to the basic solution, the tungsten material will erode away (also known in the art as xe2x80x9ccorrosionxe2x80x9d). Tungsten plugs are completely covered by the second metallization layer, however, a path remains exposing the tungsten plug. As mentioned above, because the first metallization layer and the second metallization layer are not coupled to the substrate (i.e., the structure is a floating structure), they will be positively charged and therefore the tungsten plug will erode. The erosion also varies proportionally to the potential when the pH is above a certain value. If any tungsten plugs erode, the entire IC chip may fail to operate for its intended purpose, thereby driving up fabrication costs.
Because CMOS semiconductor circuits are continuing to decrease in size, and more devices are packed into smaller IC chips, more densely integrated interconnect structures will be required. However, this dense integration has the effect of pushing the limits of conventional photolithography patterning, which necessarily makes photolithography mask misalignments more likely to occur. Of course, when more misalignments occur, more paths will result, thereby increasing the number of exposed tungsten plugs.
Chemical Mechanical Polishing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometries that are not widely isolated. CMP processes planarize the surface of semiconductor wafers to a desired thickness. In a typical CMP process, a wafer attached to a carrier is pressed against a polishing pad in the presence of a slurry. The slurry contains abrasive particles that mechanically remove material from the wafer and chemicals that chemically treat the material that is ultimately polished. Waste material eventually accumulates on the planarizing surface of the polishing pad during planarization which diminishes the pad""s effectiveness. The waste matter on the pad reduces the effectiveness and the uniformity of the planarizing surface of the polishing pad. The waste matter accordingly reduces throughput of the CMP process and the uniformity of the polished surface on the wafer. Accordingly, it is necessary to periodically clean the planarizing surface of a polishing pad. Planarizing surfaces of polishing pads are conventionally cleaned by brushing the pad with a stiff brush, but U.S. Pat. No. 5,616,069 teaches a method of using a pad scrubber to clean the planarizing surface of a polishing pad used in CMP processing of semiconductor wafers. The pad scrubber has a fluid manifold and a plurality of nozzles coupled to the manifold to clean the pad as it is used in the CMP process. U.S. Pat. No. 5,816,891 discloses a method and apparatus for performing chemical mechanical polishing of oxides and metals using sequential removal on multiple polish platens to increase equipment throughput. U.S. Pat. No. 5,852,497 to the common assignee of this patent application discusses Shallow Trench Isolation (STI) for semiconductor manufacture wherein chemical mechanical polishing (CMP) is utilized to planarize the topography of the alignment marks. Because the polysilicon layer is opaque to the conventional white light source and the HeNe source, and because the alignment marks have been planarized, boundaries between different materials are used to form the alignment marks.
In view of the foregoing, there is a need for improved CMOS fabrication techniques that prevent any exposed tungsten plugs from eroding during the basic solvent cleaning operation. Other disadvantages of prior solutions included the tungsten plug remaining intact after the solvent strip of a wafer was discharged utilizing an ionic solution, such as water. Moreover, noticeable corrosion of the aluminum lines on the semiconductor lead to less than optimal semiconductor yield. Thus, tight control of the solvent pH is very critical for successful manufacture of semiconductors to provide a persisting film of sufficient quality on the tungsten or corrosion of aluminum is likely to occur in the same range of pH.
Broadly speaking, the present invention fills these needs by providing a method that prevents exposed tungsten plugs from eroding during standard CMOS fabrication. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer is disclosed. The method includes depositing a glue layer of TiN followed by tungsten chemical vapor deposition after the contact or via is defined in the dielectric. Then, tungsten etchback or Chemical Mechanical Polishing (CMP) is performed to remove the tungsten and TiN over the dielectric surface with slight dishing of the tungsten within the plug. Next, a blanket deposition of Copper by electrochemical deposition is performed and Copper CMP is used to remove the copper from the dielectric surface while maintaining a coating of copper over the tungsten in the plug. Then, metal stack deposition, patterning and metal etching is performed and a barrier layer of silicon nitride is presented to minimize the copper diffusion. Finally, a deposition of an Interlevel Dielectric (ILD) is deposited.
The deposition of a protective material such as copper above the tungsten in the plug blocks the dissolution pathway of tungsten in the highly alkaline post metal etch strip solvent. Copper is used as an example due to its favorable characteristic of being deposited and polished commercially, and the relatively low volatility of the etch products (CuCl or CuCl2) during the metal etch whereas C12/BCl3 is the typical etch chemistry employed in semiconductor manufacturing. The deposition of silicon nitride after metal etch is essential to minimize the out-diffusion of copper into upper level dielectrics whereas the TiN glue layer minimizes the copper diffusion from the side of the vias or the contact. In addition to copper, one of ordinary skill in the art will readily comprehend that TiW could be substituted with similar results.
TiW has a lower etch rate than other substances so a barrier layer would not be necessary.
One advantage of the present invention is that very reliable interconnect structures can be fabricated without the danger of losing tungsten plugs to erosion (i.e., also known as xe2x80x9ccorrosionxe2x80x9d) in a basic solution used to remove post plasma etching polymer residues. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.